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BALD Engineering News Blog

About the Blog

Probably The Best ALD news blog. Covering new and old developments in Atomic Layer Deposition and Technology. From BALD Engineering:

jonas.sundqvist@baldengineering.com

http://www.baldengineering.com

FinFET evolution for the 7nm and 5nm CMOS technology nodes

FinFET Posted on 2014-01-23 22:51:10

FinFET evolution for the 7nm and 5nm CMOS technology nodes
From AARON THEAN, Director of the Logic Device Program at imec, Leuven, Belgium.
http://electroiq.com/blog/2014/01/finfet-evolution-for-the-7nm-and-5nm-cmos-technology-nodes/

“The learning curve to master these materials (for FinFETs) is steep. For example, introducing Ge into a fin is not a trivial process when it agglomerates easily with higher process temperatures. On the device side, leakages due to narrow band gap, gate-stack passivation, and defectivitiy are on-going hurdles. Moreover, any technique employed to integrate Ge in the pFET must be CMOS compatible, which means that it must allow a co-integration with materials for nFETS, like Si, III-V materials. For all these challenging options, it is our goal to identify, for our technology partners, the promising options, innovate on the solutions, and work-out the design/system impact”


Cross-sectional TEM images Left: SiGe on Si Fins, Middle: strained Ge/SiGe on Si, Right: InGaAs/InP on Si Fins.



A new plasma-enhanced atomic layer etch method delivers atomic-level etch precision

ALE - Atomic Layer Etching Posted on 2014-01-23 22:32:05

A new plasma-enhanced atomic layer etch method developed by LAM delivers atomic-level etch precision with process times that are practical for use in a manufacturing environment.Moving atomic layer etch from lab to fab

http://electroiq.com/blog/2014/01/moving-atomic-layer-etch-from-lab-to-fab/

“At the sub-14nm technology node, transistor performance will be highly sensitive to process variations, which can significantly impact current leakage and battery power loss. To give some perspective on the reality of the challenges, within the next 10 years, transistor gate dimensions are expected to be less than 50 atoms wide, and feature size variations will be measured in atoms, including contributions from surface roughness. Atomic layer processes are the most promising path for delivering the precision needed at this scale. Atomic layer deposition (ALD) has been in production for over a decade in the semiconductor manufacturing industry. However, it has been difficult making the etch counterpart — atomic layer etch (ALE) — productive enough for cost-effective manufacturing, and a commercially viable system has not been available. Here, we report on a plasma-enhanced ALE method using a commercial plasma reactor that provides atomic-level precision with process times that are suitable for high-volume device manufacturing.”


SEM images of polysilicon trenches etched under comparable process conditions.