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BALD Engineering News Blog

About the Blog

Probably The Best ALD news blog. Covering new and old developments in Atomic Layer Deposition and Technology. From BALD Engineering:

jonas.sundqvist@baldengineering.com

http://www.baldengineering.com

Energy Storage on Chip Integrated Supercapacitors

Capacitor Posted on 2014-01-12 15:42:30

[From Fraunhofer IPMS-CNT Web www.cnt.fraunhofer.de] The progressive miniaturization of electronic devices such as of smartphones or sensors for medical, industrial and automotive applications requires smaller substrates. This drives amongst others the integration and scaling of space consuming external passive components for buffering and decoupling purposes on chip (SoC) or package (SiP) level. Simultaneously, extremely high capacitances are needed. The main parameters to increase the capacitance are on the one side the choice of an isolator material with high dielectric constant. Several high-k materials like HfO2, ZrO2 or Ta2O5 based systems are under investigation at the Fraunhofer IPMS-CNT .

Intensive material tuning is necessary to meet the electrical requirements for capacitor applications with respect to capacitance density and linearity, leakage current and reliability. While doing this, the capacitor area has to be as large as possible andthat can be achieved by 3D integration of high aspect ratio (AR) structures.

a) SEM cross section of a trench array with AR 13:1 filled with MIM stack and b) top down micrograph of Si trench array after silicon etch.

c) TEM micrograph of a MIM stack

The Fraunhofer IPMS-CNT has developed Si-integrated high-density capacitors based on 300 mm wafer technology aiming to buffer capacitor applications. A simplified patterning scheme using e-beam lithography and high technology dry etch processes provides structures with large aspect ratio in a high package density (Figure 1a and 1b). The used capacitor stack is based on a metalinsulator-metal (MIM) structure built from Al-doped ZrO2 as dielectric and TiN electrodes. All materials are deposited by atomic layer deposition to reach highly conformal step coverage in the large aspect ratio structures (Figure 1c). The electrical characteristics show very low leakage current densities normalized for a capacitor of 1 μF. Thereby, the capacitance is stable over the voltage region with a deviation smaller than 3 %.

The temperature stability is below 5 %. These values are significantly lower compared to common ceramic capacitors. The good electrical results are complemented by a reliability over 10 years. The maximum capacitance reached for the AR of 6:1 (Gen2) lies around 100 nF/mm2 for the material system which is adapted to an operation voltage of 3 V. This is a significant increase compared to planar capacitors (Gen1).. By increasing the AR to 13:1 (Gen3) a capacitance enhancement to 220 nF/mm2 could be achieved.

The Fraunhofer IPMS-CNT forces also an up-scaling of the 3D capacitors (Gen4-5) either by an improved etch-process or by using materials with higher dielectric constant. The outlook predicts integrated capacitors of 1 μF.

Further Information can be find in this excellent pape by Wenke Weinreich et al

High-density capacitors for SiP and SoC applications based on three-dimensional integrated metal-isolator-metal structures, Weinreich, W., Rudolph, M. ; Koch, J. ;Paul, J. ; Seidel, K. ; Riedel, S. ; Sundqvist, J. ; Steidel, K. ; Gutsch, M. ;Beyer, V. ;Hohle, C. Bus. Unit Fraunhofer Center Nanoeletronic Technol., Fraunhofer Inst. of Photonic Microsyst., Dresden, Germany, 2013 IEEE International Conference onIntegrated Circuit Design



A Fully-Integrated Quartz Crystal Controller for Thin Film Deposition from Colnatec

ALD Equipment Posted on 2014-01-12 00:37:07

Housing leading-edge technology derived from Colnatec’s Eon™ frequency-temperature compensating circuitry, the Millennium™ Controller is an ultra-high resolution thin film deposition control system packaged into a standard 19-inch rackmount enclosure and featuring a versatile touch screen display.

Incorporating the same technology as the Eon-LT™, the Millennium™ offers a temperature measuring film thickness controller built into a modular framework. The Millennium™ controller, which is designed with the same level of dependability and precision of all Colnatec products, supports up to four sources and sensors (2 standard), co-deposition functionality, real-time frequency-temperature curve generation, and 500°C crystal operation.

Here are all the details: LINK



The follow up to Google Glass could soon be here “Google lens”

Technology Posted on 2014-01-12 00:23:44

Researchers at the Swiss Federal Institute of Technology in Zurich (ETH Zurich) have created clear, flexible electronic circuitry that is so thin it can sit upon the surface of a contact lens, or be wrapped around a human hair according to Gizmag.com. The research, led by Dr. Giovanni Salvatore, could ultimately be used for implantable medical devices. One such potential application suggested by the team is a “smart contact lens” that could monitor intraocular pressure for glaucoma patients.

In order to create the circuits, the layers are deposited using e-beam evaporation, atomic layer deposition, spin coating and radio frequency sputtering. The structuring is created using ultraviolet (UV) lithography and etching. The circuits are created on a substance called parylene, an insulator that is traditionally used as a protective coating for electronic devices and components.

The circuitry is so thin it can sit on top of a contact lens, or be wrapped around a human hair

Continue reading the complete story in Gizmag.



The 12th International Baltic ALD conference will be held May 12-13, 2014 in Helsinki, Finland

Conferences Posted on 2014-01-12 00:13:18

2014 it is 40 years since Dr. Tuomo Suntola filed his famous patent on ALE!

[information from Finnish Centre of Excellence in Atomic Layer Deposition – http://www.aldcoe.fi/bald2014/]

The conference is a continuation of a series of meetings that started in 1991 in Espoo as a Helsinki University of Technology – Tartu University ALE symposium, followed by a symposium in Tartu in 1993. In 1995 the meeting was organized by University of Helsinki and at that time the name was broadened to Baltic ALE symposium. In 1997 in Tartu it adopted its present name and has subsequently circled around the Baltic Sea in Uppsala, Oslo, Warsaw and Hamburg besides Finland and Estonia.

Invited Speakers:

Professor Jaan Aarik, University of Tartu, Estonia
Professor Victor Drozd, St. Petersburg State University, Russia
Professor Marc Heyns, IMEC, Belgium
Professor Kornelius Nielsch, University of Hamburg, Germany
Professor Shi-Woo Rhee, POSTECH, Korea
Professor Xueliang (Andy) Sun, The University of Western Ontario, Canada
Dr. Jonas Sundqvist, Fraunhofer CNT, Germany
Dr. Tuomo Suntola, Picosun Ltd., Finland
Professor Roger Webb, University of Surrey, England
Important dates:

Online Abstract Submission Open : December 2, 2013
Deadline for Abstract Submission : January 31, 2014
Online Registration and Hotel Accommodation Open : January 1, 2014
Notification of Acceptance : March 15, 2014
Deadline for Online Registration : April 17, 2014

NB! The abstract submission deadline has been extended by one week till February 7, 2014



2014.03.24 – NaMLab, The Novel High k Application Workshop

Workshops Posted on 2014-01-12 00:11:16

Hörsaal TU Dresden Fakultät Informatik: http://www.inf.tu-dresden.de/index.php?node_id=12&ln=de

Nöthnitzer Straße 46 D-01187 Dresden

(between Namlab and the MPI last year)

Preliminary Program for the Workshop coming soon



2014.02.06 – The 4th IPMS-CNT Industry Partner Day

Workshops Posted on 2014-01-12 00:02:42

Fraunhofer IPMS-CNT cordially invite to “Nanoelectronic Technologies for Future Smart Systems” in Dresden. This time with high-level speakers from Globalfoundries, IBM, Infineon, IMEC and JSR Mirco. Full program and online registration behind the link.

Get Together & CNT Clean Room Window Tour (limited capacity!)

http://www.cnt.fraunhofer.de/en/Events_Press/events_trade_fairs/cnt_research_day12.html

Programm & Schedule:

8:30 a.m. -Registration-
9:00 a.m. WelcomeProf. Dr. Hubert Lakner, Director Fraunhofer IPMS, Chairman Fraunhofer Group Microelectronics
9:15 a.m. Cooperation is Key – R&D perspectives at Globalfoundries Dresden, Dr. Manfred Horstmann, Director Technology & Integration, Device – Globalfoundries
9:45 a.m. Made in Dresden – Infineon Today & Tomorrow, Dr. Norbert Thyssen, Director Customer Services / Dvmt. Projects – Infineon
10:15 a.m. Coffee Break

Session: Devices in Back-End-of-Line

10:40 a.m.Challenges for 28 nm BEOL, Thomas Werner, Manager Technology & Integration Engineering – Globalfoundries
11:05 a.m. Chemical screening for CMP applications, Peter Bridger, CMP Project Manager – JSR Micro, Belgium
11:30 a.m. CNT as test bed for chemical screening, Dr. Benjamin Uhlig, Fraunhofer IPMS-CNT Interconnects
11:55 a.m. High-k 3DMIM-Cap Devices, Dr. Wenke Weinreich, Fraunhofer IPMS-CNT High-k Devices
12:20 p.m.-Lunch Break-

Session: Logic & Memory Scaling

1:00 p.m. New front-end materials for continued CMOS logic scaling, Dr. Martin M. Frank, BM Research/New York
1:25 p.m. RRAM – Challenges and Opportunities of an Emerging Memory, Dr. Malgorzata Jurczak, Director Emerging Memory Devices – IMEC Belgium
1:50 p.m. A CMOS-compatible and highly scalable approach to future ferroelectric memories, Johannes Müller, FraunhoferIPMS-CNT High-k Devices)
2:15 p.m. -Short Coffee Break-

Session: MEMS, Passives & Nanopatterning

2:25 p.m. Nanopatterning using alternative Litho, Dr. Christoph Hohle, Fraunhofer IPMS-CNT Nanopatterning
2:50 p.m. MEMS-Technology at Fraunhofer IPMS, Dr. Michael Müller, IPMS MEMS Sensors)
3:15 p.m. -End of Program-